Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type.
One of the problems facing the manufacturability of semiconductor floating gate memory cell arrays has been the alignment of the various components such as source, drain, control gate, and floating gate. As the design rule of integration of semiconductor processing decreases, reducing the smallest lithographic feature, the need for precise alignment becomes more critical. Alignment of various parts also determines the yield of the manufacturing of the semiconductor products.
Self-alignment is well known in the art. Self-alignment refers to the act of processing one or more steps involving one or more materials such that the features are automatically aligned with respect to one another in that step processing. Accordingly, the present invention uses the technique of self-alignment to achieve the manufacturing of a semiconductor memory array of the floating gate memory cell type.
There is a constant need to shrink the size of the memory cell arrays in order to maximize the number of memory cells on a single wafer. It is well known that forming memory cells in pairs, with each pair sharing a single source region, and with adjacent pairs of cells sharing a common drain region, reduces the size of the memory cell array. However, a large area of the array is typically reserved for the bit-line connection to the drain regions. The bit-line area is often occupied by the contact openings between memory cell pairs, and the contact to wordline spacing, which strongly depends upon lithography generation, contact alignment and contact integrity. In addition, significant space is reserved for the word-line transistor, the size of which is set by lithography generation and junction scaling.
Traditionally, floating gates are formed with a sharp edge facing a control gate to enhance Fowler-Nordheim tunneling, which is used to move electrons off of the floating gate during an erase operation. The sharp edge is typically formed by oxidizing or partially etching the top surface of the floating gate poly in an uneven manner. However, as the dimensions of the floating gate get smaller, this sharp edge can be more difficult to form in this manner.
There is also a need to improve the programming efficiency of memory cell array. Referring to FIG. 10A, there is shown a partial cross sectional view of a flash memory cell 200 of the prior art (as disclosed in U.S. Pat. No. 5,029,130, whose disclosure is incorporated herein by reference in its entirety). During programming, region 210 is held at or near ground voltage. Region 220 is supplied with a high voltage such as +10 volts. A depletion region 250 is then formed about the region 220. Further, because of the high capacitive coupling between region 220 and the floating gate 230, the floating gate 230 “sees” a voltage of approximately +7 volts. A voltage slightly more positive than the threshold voltage, such as +1.5 volts, is applied to the control gate 240. Since the voltage at the control gate 240 is less than the voltage at the floating gate 230, the field lines will emanate from the floating gate 230 to the substrate 260, and then to the control gate 240. When a positive voltage is applied to the control gate 240, the portion of the channel region beneath the control gate 240 is “turned on”, i.e. an inversion layer 280 is formed. Electrons flow from the first region 210 near the surface of the substrate 260 in the inversion layer 280 until it reaches the pinch off point 295. At that point 295, the electrons are accelerated by the field lines. However, in order to “inject” electrons onto the floating gate 230, the electrons from the first region 210 must collide with (i.e. scatter) either impurities or lattice imperfections in the substrate 260 to generate momentum in the vertical direction. Further, only those electrons having sufficient vertical velocity to overcome the energy barrier between the oxide and the silicon will be injected onto the floating gate 230. As a result only a small percentage of electrons (on the order of 1 in a 1000) from the electron current in the inversion layer 280 will have sufficient energy to be injected onto the floating gate 230. Therefore, in this mechanism of programming, scattering is an essential component of the programming mechanism.
Referring to FIG. 10B there is shown another programming mechanism of the prior art involving an EPROM cell 300. Similar to the discussion for the flash cell 200 shown in FIG. 10a, during programming, first region 210 is held at or near ground voltage. Region 220 is supplied with a high voltage such as +12 volts. A depletion region 250 is then formed about the second region 220. A high voltage, such as +12 volts is also applied to the control gate 240, which results in the floating gate 230 “seeing’ about +7 volts. Since the voltage on the floating gate 230 is less than the voltage at the depletion region 250, the field lines will emanate from the depletion region 250 to the floating gate 230. Further, with the floating gate “seeing” about +7 volts, the portion of the channel region beneath the floating gate 230 is “turned on”, i.e. an inversion layer 280 is formed. Electrons flow from the first region 210 near the surface of the substrate 260 in the inversion layer 280 until it reaches the pinch off point 295. At that point 295, the electrons are accelerated by the field lines. However, the electrons are actually repulsed from the surface of the substrate 260 by the field lines. As a result the electrons travel in a “downward” direction. In order to “inject” electrons onto the floating gate 230, the electrons from the first region 210 must collide with either impurities or with the lattice imperfections in the substrate 260 to generate vertical component of momentum. Only those electrons having sufficient initial vertical velocity and then sufficiently in the upward vertical direction to overcome the 1) repulsive field in the substrate; 2) energy barrier at the silicon-oxide interface; and 3) repulsive field in the oxide will be injected onto the floating gate 230. As a result because initially the electrons are actually traveling “downward” a fewer percentage of electrons than even the percentage of electrons in the flash cell 200 are programmed (on the order of 1 in hundreds of thousands or even a million from the electron current in the inversion layer 280 will have sufficient energy to be injected onto the floating gate 230. Thus, similarly, in this mechanism of programming, scattering is an essential component of the programming mechanism.
Thus it is one object of the present invention to create a method to improve the programming efficiency of a non-volatile memory cell having a floating gate for storage of electrons.
It is known to form memory cell elements over non-planar portions of the substrate. For example, U.S. Pat. No. 5,780,341 (Ogura) discloses a number of memory device configurations that includes a step channel formed in the substrate surface. While the purpose of the step channel is to inject hot electrons more efficiently onto the floating gate, these memory device designs are still deficient in that it is difficult to optimize the size and formation of the memory cell elements as well the necessary operational parameters needed for efficient and reliable operation.
There is a need for a non-volatile, floating gate type memory cell array with significant cell size reduction while providing enhanced programming efficiency.